Cached Dram Adds a Small Cache onto a Dram Chip to Reduce Average Dram Access Latency. the Authors Compare Cached Dram with Other Advanced Dram Techniques for Reducing Memory

As the speed gap between processor and memory widens, data-intensive applications such as commercial workloads increase demands on main memory systems. Consequently, memory stall time—both latency time and bandwidth time—can increase dramatically, significantly impeding the performance of these applications. DRAM latency, or the minimum time for a DRAM to physically read or write data, mainly determines latency time. The data transfer rate through the memory bus determines bandwidth time. Burger, Goodman, and Kägi show that memory bandwidth is a major performance bottleneck in memory systems. More recently, Cuppu et al. indicate that with improvements in bus technology, the most advanced memory systems, such as synchronous DRAM (SDRAM), enhanced SDRAM, and Rambus DRAM, have significantly reduced bandwidth time. However, DRAM speed has improved little. DRAM speed is a major factor in determining memory stall time, which significantly affects the performance of data-intensive applications such as commercial workloads. In a cached DRAM, a small or on-memory cache is added onto the DRAM core. The onmemory cache exploits the locality that appears on the main memory side. The DRAM core can transfer a large block of data to the on-memory cache in one DRAM cycle. This data block can be several dozen times larger than an L2 cache line. The on-memory cache takes advantage of the DRAM chip’s high internal bandwidth, which can be as high as a few hundred gigabytes per second. Hsu and Smith classify cached DRAM organizations into two groups: those where the on-memory cache contains only a single large line buffering an entire row of the memory array, and those where the on-memory cache contains multiple regular data cache lines organized as direct-mapped or set-associative structures. In a third class combining these two forms, the on-memory cache contains multiple large cache lines buffering multiple rows of the memory array organized as direct-mapped or set-associative structures. Our work and other related studies belong to this third class. Cached DRAM improves memory access efficiency for technical workloads on a relatively simple processor model with small data caches (and in some cases, even without data caches). In a modern computer system, the CPU is a complex instruction-level parallelism Zhao Zhang, Zhichun Zhu, and Xiaodong Zhang